The rapidity at which the device integration density has progressed in recent years in semiconductor IC devices is remarkable, and the pattern line width has been reduced to the order of sub-microns. Consequently, the required high accuracy of mask alignment in photolithography for the manufacturing of semiconductor devices impedes further miniaturization of semiconductor devices.
The source/drain regions of a MOS transistor have been difficult to miniaturize. The reason for this is that the accuracy of mask alignment at the time of formation of the electrodes of the source/drain regions, which governs the occupation areas of the regions, could not be attained to the required degree. It has heretofore been difficult to miniaturize the device occupation areas.
There have been proposed methods for realizing a high integration density for the electrode portions by forming the electrode portions in a self-aligned fashion. An example is the method disclosed in JP-B-5-81051 (published on Nov. 11, 1993) corresponding to JP-A-62-291176 (laid-open on Dec. 17, 1987).
The problem with the conventional manufacturing method is that it requires many manufacturing steps to form electrodes of diffused layers (source/drain regions), including the steps of (a) depositing a molybdenum film on a poly-silicon film, (b) causing an impurity in a poly-silicon film to diffuse into the poly-silicon to form an impurity-doped poly-silicon film, and (c) a heat treatment for making the molybdenum film react with the impurity-doped poly-silicon film. This, however, tends to decrease the throughput and production yield.